GBTX LTB

Document #:

CMS-doc-5946-v7

Document type:

Technical Data

Submitted by:

Tullio Grassi

Updated by:

Tullio Grassi

Document Created:

13 Mar 2012, 13:29

Contents Revised:

31 Jul 2013, 15:19

Metadata Revised:

31 Jul 2013, 15:19

Abstract:

The Link Test Board (LTB) is part of the setup for the test of the GBTX ASIC

Files in Document:

• Specifications (Specs_of_GBTX_test_cards.docx, 137.7 kB)
• Zipped Altium design project (GBTX-LTB (03-Jul-12 2-50-15 PM).zip, 4.9 MB)
• Zipped Xilinx design project (GBTX_LTB.zip, 6.7 MB)
• pdf of schematics, PCB and BOM (GBTX-LTB.pdf, 1.4 MB)

Other Files:

• GBTX_test_setup1.jpg (367.5 kB)
• Comments from David Porret. (GBTX_LTB_review_by_David.txt, 1.9 kB)
• Verilog Virtex-6 FPGA project, no GigE (GBTX_LTB_v3_9_0.zip, 2.2 MB)
• pinout of connector to Load board, by David Porret. (Loadboard_Testboard_Interface.xlsx, 35.1 kB)

Topics:

• Upgrades:General Technical Information

Authors:

• Tullio Grassi

Related Documents:

• CMS-doc-3857: GBTX specifications
• CMS-doc-4801: Specifications for Small Form Factor Pluggable Module SFP+
• CMS-doc-4802: Versatile TransReceiver (VTRx) and Twin-Transmitter (VTTx) modules.

Publication Information:

https://edms.cern.ch/nav/P:EDA-02180:V0/I:EDA-02180-V2-0:V0/TAB4