GBTX LTB

Document #:

CMS-doc-5946-v5

Document type:

Technical Data

Submitted by:

Tullio Grassi

Updated by:

Tullio Grassi

Document Created:

13 Mar 2012, 13:29

Contents Revised:

13 Jun 2012, 10:53

Metadata Revised:

12 Sep 2012, 12:04

Abstract:

The Link Test Board (LTB) is part of the setup for the test of the GBTX ASIC

Files in Document:

• Specifications (Specs_of_GBTX_test_cards.docx, 137.7 kB)
• Zipped Altium design project (GBTX-LTB_Tullio.zip, 4.5 MB)
• Zipped Xilinx design project (GBTX_LTB.zip, 6.7 MB)
• pdf of schematics, PCB and BOM (GBTX-LTB_Tullio.pdf, 4.0 MB)

Other Files:

• Comments from David Porret. (GBTX_LTB_review_by_David.txt, 1.9 kB)
• Virtex-6 FPGA project, first version, for validation of schematics (GBTX_LTB_8Jun2012.zip, 6.7 MB)
• pinout of connector to Load board, by David Porret. (Loadboard_Testboard_Interface.xlsx, 35.1 kB)

Topics:

• Upgrades:General Technical Information

Authors:

• Tullio Grassi

Notes and Changes:

Four PCB manufactured at the beginning of August. Two cards assembled by the Cern shop at the end of August 2012.
During testing found missing connections to 2V5 on the Ethernet part J11, pins TRCT1, 2, 3, 4. This is easy to correct on the board.

Related Documents:

• CMS-doc-3857: GBTX specifications
• CMS-doc-4801: Specifications for Small Form Factor Pluggable Module SFP+
• CMS-doc-4802: Versatile TransReceiver (VTRx) and Twin-Transmitter (VTTx) modules.

Publication Information:

https://edms.cern.ch/nav/P:EDA-02180:V0/I:EDA-02180-V2-0:V0/TAB4