CMS Document 3327-v15

HCAL Trigger Readout module (HTR) Revision 4 Design Documentation

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Abstract:: HCAL Trigger Readout module (HTR) Revision 4 Design Documentation

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0402_shorted1.jpg (1.1 MB)
0402_shorted2.JPG (843.0 kB)
9760HTRRev4.3Specs.txt (1.8 kB)
9760HTRStackup.pdf (23.2 kB)
BAD_R198_close.JPG (1.5 MB)
CMS HTR Rev4 status.htm (21.9 kB)
ChangesToRev4.txt (4.1 kB)
Data_format_v2.pdf (30.6 kB)
FPGAChangesToRev4.txt (4.3 kB)
Finished.JPG (629.8 kB)
FinishedZoom.JPG (288.4 kB)
Fuse_fix.html (5.2 kB)
HTRMainFPGA_r4_series2.dat.txt (62.9 kB)
HTRRev4_3_CAD.zip (7.2 MB)
HTR_MainFPGA.ppt (1021.5 kB)
HTR_ProductionSchematics.pdf (3.2 MB)
HTR_RCT_integ.html (2.2 kB)
HTR_Rev4.1_sch.pdf (3.2 MB)
HTR_Rev4_sch.pdf (2.7 MB)
HTR_r4_series1.dat.txt (5.7 kB)
HTRev4_Mechanics.pdf (1.0 MB)
HTRev4_checkout.html.old.html (13.2 kB)
Hook.JPG (687.7 kB)
HookZoom.JPG (683.5 kB)
KerpenMegaLineCable727.pdf (67.9 kB)
KnownProblemOnTheAssembledBoards.txt (1.2 kB)
MTP_Std_Plastic_Adapter.pdf (39.3 kB)
Rev3_Latency_measure.pdf (11.2 kB)
Rev3_Latency_measure_prelim.pdf (11.2 kB)
Rev4MainFPGA.pdf (333.7 kB)
Rev4MainFPGA.ppt (727.0 kB)
Stratos_M2R_25_9_X_TXL.pdf (200.2 kB)
U117_shorted1.JPG (1.1 MB)
U117_shorted2.JPG (1.1 MB)
Xilinx_addr_Rev4.html (88.2 kB)
Xilinx_addr_Rev4_26APR07.html (88.3 kB)
Xilinx_addr_Rev4_bak.html (122.5 kB)
checkout_HTRev4.html (81.3 kB)
checkout_HTRev4.html.30MAY2008.html (79.7 kB)
checkout_HTRev4.html_bak.html (19.3 kB)
htr4_Bom_files.zip (26.2 kB)
htr4_bom.html (11.4 kB)
requirements.txt (3.1 kB)
tlk2501.pdf (336.0 kB)
proposed data format for LHC 2012 run (Short_Term_DataFormatChange_2.pdf, 41.9 kB)

Publication Information:: http://cmsdoc.cern.ch/cms/HCAL/document/CountingHouse/HTR/HTR_index.html