From: Tullio Grassi Date: Fri, Mar 23, 2012 at 4:49 PM Subject: Re: GBTX Link Test Card To: David Porret Thanks a lot, see my comments below: On Fri, Mar 23, 2012 at 2:27 PM, David Porret wrote: > Here are some comments : > On pdf page 3 , connector J8D , pins 13D + 14D are connected to ground ok! please check the updated schematics, on the same URL. > From the schematic I understand that 2 power supplies channels are ganged is it > correct ? Otherwise there is a problem with the power supplies. the only power voltage needed by the board is +5V, so I was thinking to gang power supplies at 5V. I hope it does not create any conflict. > For the utility bits, you need to setup one of the THIF power supply, in your case the +3.3V > as the FPGA is powered in 2.5V. > So the sense lines p33_S+/S- have to be connected to the Force/Return pins. > The p33_F is not used but the p33_R needs to be connected to GND. ok! please check the updated schematics, on the same URL. > According to Credence the part behind the utility bits is this one Micrel MIC59P60. > For the debugging , I would put few LEDs more and 4 small coaxial connectors (LEMO or SMA) to trigger a scope or check some signals from the FPGA with 51R in serie to get clean signals. ok, I have added four SMA: J12-J15. About the LEDs, there were already a few LEDs in the other pages (for power and for the SFP+ and VTRX). The total is 11 LEDs. Thanks, Tullio > > -----Original Message----- > From: Tullio Grassi [mailto:tullio.grassi@gmail.com] > Sent: 20 mars 2012 12:41 > To: David Porret > Subject: GBTX Link Test Card > > Hi David, > > when you have time, can you look at my schematics, especially the > connections to the HD Mezz, like power, clocking, etc ? > They are on: > https://cms-docdb.cern.ch/cgi-bin/PublicDocDB//ShowDocument?docid=5946 > > Thanks, > > Tullio